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Freehdl
Jul 20, 2023
Free VHDL simulator
The goals of the FreeHDL project are to develop a VHDL simulator that has a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage.
Checkout these related ports:
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- Z88 - Compact Finite Element Analysis System
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- Yosys-systemverilog - SystemVerilog support for Yosys
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