Veryl

Jul 20, 2023

Veryl: A modern Hardware Description Language (HDL)

Veryl is a modern hardware description language.

This project is under the exploration phase of language design.

Features

  • Symplified syntax
    • Based on SystemVerilog / Rust
  • Transpiler to SystemVerilog
    • Human readable output
    • Interoperability with SystemVerilog
  • Integrated Tools
    • Semantic checker
    • Source code formatter
    • Language server


Checkout these related ports:
  • Zcad - Simple CAD program
  • Z88 - Compact Finite Element Analysis System
  • Yosys - Yosys Open SYnthesis Suite
  • Yosys-systemverilog - SystemVerilog support for Yosys
  • Xyce - Xyce electronic simulator
  • Xcircuit - X11 circuit schematics drawing program
  • Veroroute - PCB (printed circuit board) design software
  • Verilog-mode.el - Emacs lisp modules for the Verilog language
  • Verilator - Synthesizable Verilog to C++ compiler
  • Uranium - Python framework for 3D printing applications
  • Uhdm - Universal Hardware Data Model
  • Tochnog - Free explicit/implicit Finite Element Program
  • Tkgate - Event driven digital circuit simulator
  • Sweethome3d - Free interior 3D design application
  • Svls - SystemVerilog language server