py311-verilog_parser
0.0.7Lark-based parser for structural Verilog netlists
Lark-based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.
Origin: cad/py-verilog-parser
Category: cad
Size: 88.0KiB
License: AGPLv3+
Maintainer: spaciouscoder78@disroot.org
Dependencies: 1 packages
Required by: 0 packages
Website: codeberg.org/tok/py-verilog-parser
$
pkg install py311-verilog_parserDependencies (1)
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