surelog
1.84SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
Origin: cad/surelog
Category: cad
Size: 15.4MiB
License: APACHE20
Maintainer: yuri@FreeBSD.org
Dependencies: 4 packages
Required by: 0 packages
Website: github.com/chipsalliance/Surelog
$
pkg install surelogDependencies (4)
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