veryl
0.17.2Veryl: A modern Hardware Description Language (HDL)
Veryl is a modern hardware description language. This project is under the exploration phase of language design. Features: * Symplified syntax * Based on SystemVerilog / Rust * Transpiler to SystemVerilog * Human readable output * Interoperability with SystemVerilog * Integrated Tools * Semantic checker * Source code formatter * Language server
Origin: cad/veryl
Category: cad
Size: 27.4MiB
License: MIT, APACHE20
Maintainer: yuri@FreeBSD.org
Dependencies: 0 packages
Required by: 0 packages
Website: github.com/dalance/veryl
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