Ghdl

Jul 20, 2023

GNU VHDL simulator

GHDL is the leading VHSIC Hardware Description Language VHDL simulator.

Digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits can be described by VHDL, and VHDL can also be used as a general purpose parallel programming language. GHDL compiles VHDL files and creates a binary which simulates the design.

GHDL fully supports IEEE 1076-1987, IEEE 1-76-1993, IEEE 1076-2002 versions of VHDL, and partially IEEE 1076-2008.



Checkout these related ports:
  • Zcad - Simple CAD program
  • Z88 - Compact Finite Element Analysis System
  • Yosys - Yosys Open SYnthesis Suite
  • Yosys-systemverilog - SystemVerilog support for Yosys
  • Xyce - Xyce electronic simulator
  • Xcircuit - X11 circuit schematics drawing program
  • Veryl - Veryl A modern Hardware Description Language (HDL)
  • Veroroute - PCB (printed circuit board) design software
  • Verilog-mode.el - Emacs lisp modules for the Verilog language
  • Verilator - Synthesizable Verilog to C++ compiler
  • Uranium - Python framework for 3D printing applications
  • Uhdm - Universal Hardware Data Model
  • Tochnog - Free explicit/implicit Finite Element Program
  • Tkgate - Event driven digital circuit simulator
  • Sweethome3d - Free interior 3D design application