RECENT POSTS

Do you have GDPR compliance issues ?

Check out Legiscope a GDPR compliance software, that will save you weeks of work, automating your documentation, the training of your teams and all processes you need to keep your organisation compliant with privacy regulations

Qflow

Jul 20, 2023

End-to-end digital synthesis flow for ASIC designs

A digital synthesis flow is a set of tools and methods used to turn a circuit design written in a high-level behavioral language like verilog or VHDL into a physical circuit, which can either be configuration code for an FPGA target like a Xilinx or Altera chip, or a layout in a specific fabrication process technology, that would become part of a fabricated circuit chip. Several digital synthesis flows targeting FPGAs are available, usually from the FPGA manufacturers, and while they are typically not open source, they are generally distributed for free presumably on the sensible assumption that more people will be buying more FPGA hardware.

Checkout these related ports:
  • Zcad - Simple CAD program
  • Z88 - Compact Finite Element Analysis System
  • Yosys - Yosys Open SYnthesis Suite
  • Yosys-systemverilog - SystemVerilog support for Yosys
  • Xyce - Xyce electronic simulator
  • Xcircuit - X11 circuit schematics drawing program
  • Veryl - Veryl A modern Hardware Description Language (HDL)
  • Veroroute - PCB (printed circuit board) design software
  • Verilog-mode.el - Emacs lisp modules for the Verilog language
  • Verilator - Synthesizable Verilog to C++ compiler
  • Uranium - Python framework for 3D printing applications
  • Uhdm - Universal Hardware Data Model
  • Tochnog - Free explicit/implicit Finite Element Program
  • Tkgate - Event driven digital circuit simulator
  • Sweethome3d - Free interior 3D design application