Yosys Open SYnthesis Suite
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
$
pkg install yosysOrigin
cad/yosys
Size
30.7MiB
License
ISCL
Maintainer
yuri@FreeBSD.org
Dependencies
9 packages
Required by
3 packages