SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.
$
pkg install surelogOrigin
cad/surelog
Size
15.4MiB
License
APACHE20
Maintainer
yuri@FreeBSD.org
Dependencies
4 packages
Required by
0 packages