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Uhdm
Jul 20, 2023
Universal Hardware Data Model
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools.
libuhdm implements the hardware object model standardized in IEEE 1800.1-2017 chapter 37 VPI object model.
Checkout these related ports:
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